With the rapid development of integrated circuit (IC) technology, the size of the semiconductor devices of ICs, especially the metal oxide semiconductor (MOS) devices, has become smaller and smaller to match the requirements of device miniaturization and integration. When the size of the MOS transistor is continually shrunk, the process using the gate dielectric layer made of silicon oxide or silicon nitride meets certain challenges. For example, the transistors having the gate dielectric layer made of silicon oxide and silicon nitride face certain problems, such as the increase of leakage current, and/or the diffusion of the impurities, etc. Such problems may affect the threshold voltage of the transistors; and the performance of the semiconductor devices may be significantly affected.
In order to solve the above-mentioned problems, a high-K metal gate (HKMG) structure) has been introduced into the MOS transistors. The HKMG structure utilizes a high dielectric constant (high-K) material to substitute the conventionally used gate dielectric material, such as silicon oxide and silicon nitride, etc. The HKMG structure may reduce the leakage current of the transistor when the size of the transistor is reduced; and the performance of the transistor may be improved as well.
FIG. 1 illustrates an existing transistor having a high-K metal gate (HKMG) structure. As shown in FIG. 1, the transistor includes a semiconductor substrate 100 having a dielectric layer 105 and a gate structure 110. The top surface of the gate structure 110 levels with the top surface of the dielectric layer 105. The gate structure 105 includes a high-K dielectric layer 101 formed on the surface of the semiconductor substrate 100, a metal gate 103 formed on the surface of the high-K dielectric layer 101; and a sidewall spacer 104 formed on the side surface of the high-K dielectric layer 101 and the metal gate 103; and source/drain regions 106 formed in the semiconductor substrate 100 at both sides of the gate structure 110.
The HKMG structure 110 may be formed by a gate-last process. FIGS. 2-4 illustrate semiconductor structures corresponding to certain stages of an existing fabrication process of the transistor illustrated in FIG. 1. As shown in FIG. 2, the process includes providing a semiconductor substrate 100 and forming a dummy gate 120 on the surface of the semiconductor substrate 100. The dummy gate 120 includes a dummy gate dielectric layer 121 formed on the surface of the semiconductor substrate 100; a dummy gate layer 122 formed on the surface of the dummy gate dielectric layer 122, and the sidewall spacer 123 formed on the surface of the semiconductor substrate 100 at both sides of the dummy gate dielectric layer 121 and the dummy gate layer 122. A dielectric layer 105 may be formed on the surface of the semiconductor substrate 100; and the surface of the dielectric layer 105 levels with the surface of the dummy gate layer 122. Further, as shown in FIG. 3, after forming the dummy gate 120, the dummy gate layer 122 is removed; and an opening 124 is formed in the dielectric layer 105. Further, as shown in FIG. 4, after forming the opening 124, the dummy gate dielectric layer 122 on the bottom of the opening 124 may be removed.
The dummy gate layer 122 is usually made of poly silicon, and the semiconductor substrate 100 is usually made of silicon, thus the etching selectivity between the dummy gate layer 122 and the semiconductor substrate 100 may be very poor. In order to prevent the surface of the semiconductor substrate 100 from being damaged by a process for removing the dummy gate layer 122, the dummy gate dielectric layer 121 is formed between the semiconductor substrate 100 and the dummy gate layer 122. The dummy gate dielectric layer 121 is made of silicon oxide; and is formed by a thermal oxidation process. The silicon oxide layer formed by the thermal oxidation process may have a significantly high adhesion with the semiconductor substrate 100, thus it may aid the subsequent processes. However, the equivalent oxide thickness (EOT) of the silicon oxide layer formed by the thermal oxidation process may be relatively large, with the continuously shrinking of the size of the semiconductor devices; the dummy gate dielectric layer 121 on the bottom of the opening 124 may have adverse effect onto the subsequently formed transistors. Further, it may be difficult to control the thickness of the dummy gate dielectric layer 121 after removing the dummy gate layer 122. Therefore, after removing the dummy gate layer 122, the dummy gate dielectric layer 121 may need to be removed to expose the surface of the semiconductor substrate 100 so as to subsequently form an pad oxide layer, a gate dielectric layer and a gate electrode layer on the surface of the substrate 100 on the bottom of the opening 124.
However, the dielectric layer 105 is also usually made of silicon oxide, thus when the dummy gate dielectric layer 121 is removed, the dielectric layer 105 is also be thinned; and the sidewall spacer 123 is also etched with a certain thickness. Therefore, the surfaces of the dielectric layer 105 and the sidewall spacer 123 are not smooth and even. After subsequently forming high-K dielectric material and metal material in the opening 124, a polishing process may need to remove the dielectric material and the metal material on the dielectric layer 105. Because the surface of the dielectric layer 105 is not smooth and even, metal residues may be formed on the surface the dielectric layer 105 and the top surface of the sidewall spacer 123. Such residues may promote to form leakage current on the top of the metal gate 120; and the performance of the transistors may be significantly affected.
The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.